Speed, component count, and accuracy are important considerations in designing an A/D converter. Parallel converters provide the greatest speed in converting an analog input voltage (generally referred to as "37 V.sub.I ") into an n-bit digital code. A typical parallel A/D converter, such as that described in Nordstrom et al, UK Pat. No. 1,547,918, or Fujita, EPO Publication 120,424, has 2.sup.n input comparators for comparing V.sub.I with a like number of reference voltages.
The comparators are differential devices. For example, each comparator in Nordstrom et al employs a pair of NPN transistors whose emitters are tied to a current source. The bases of the pair follow V.sub.I and a corresponding one of the reference voltages. The collectors provide complementary signals on a pair of lines connected to respective load elements. Each comparator is in one of two states. As V.sub.I traverses an input voltage range in one direction, a progressively greater number of the comparators provide outputs representing a particular one of the states.
A logic network operates on the "thermometer" output supplied by the comparators to generate 2.sup.n circuit signals. Each circuit signal is normally logical low and reaches logical high only when V.sub.I is in a designated portion of the input range. The designated portion for each signal is separate from (i.e., does not overlap) the designated portion for each other signal. The designated portions are also spread out at approximately equal intervals across the input range. In this way, all the circuit signals are low at any time except for the one corresponding to the current value of V.sub.I.
A code converter transforms the circuit signals into the digital code which is supplied on n output lines. In Nordstrom et al, the code converter consists of 2.sup.n NPN transistors. Each has one or more emitters connected selectively to the output lines according to the desired coding. The code converter in Fujita is an array of like-polarity field-effect transistors (FET's) whose sources are grounded. The drains of the FET's are selectively connected to the output lines. Since the code converter in Fujita or Nordstrom et al is single ended, a reference must be used to determine whether each bit of the output code is logical low or logical high.
The main disadvantage of a parallel A/D converter is a high component count due to the large number of input comparators. The device requires a large chip area when implemented as an integrated circuit.
One of the more promising means for cutting component count is a "folding" system. See: van de Grift et al, "A Monolithic 8-Bit Video A/D Converter," IEEE JSSC, June 1984, pp. 374-378; and van de Plassche et al, "A High-Speed 7 Bit A/D Converter," IEEE JSSC, Dec. 1979, pp. 938-943. As described in each of these references, a folding A/D converter contains a coarse parallel A/D converter, a folding circuit, and a fine parallel A/D converter. The coarse converter operates directly on V.sub.I to generate the m most significant bits of the digital code. The folding circuit contains a set of input amplifiers that compare V.sub.I with at least four different reference voltages supplied from a voltage divider. The amplifiers are interconnected in such a way as to directly generate one or more pairs of complementary waveforms having a repetitive rounded triangular shape as a function of V.sub.I. Extreme values of each waveform occur at V.sub.I values dependent on selected ones of the reference voltages. The fine converter operates on these waveforms to produce the remaining n-m bits.
A folding A/D converter utilizes considerably less comparators, including input amplifiers, than an equivalent parallel converter. Chip area is reduced dramatically. However, generation of the repetitive rounded triangular waveforms in the unitary way described above makes the folding converter unduly sensitive to noise. It would be desirable to have a simple technique for overcoming this problem.